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ISD14B00 publication release date: jan 19, 2009 revision 0.30 30 ISD14B00 31 single-chip, multiple-message 32 voice record/playback device www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 revision 0.30 table of contents 1. general description ............................................................................................................................... 3 2. features .......................................................................................................................................................3 3. block diagram ............................................................................................................................................5 4. pin description ..........................................................................................................................................6 5. functional description .........................................................................................................................9 5.1 address mode ........................................................................................................................................... 9 5.1.1. record ( rec ) operation ................................................................................................................. 10 5.1.2. edge-triggered playback ( playe ) operation ................................................................................... 12 5.1.3. level-triggered playback ( playl ) operation ................................................................................... 12 5.1.4. playback (supersedes record) operation ...................................................................................... 13 5.1.5. xclk feature ............................................................................................................................... ... 14 5.2. direct mode ............................................................................................................................... .............. 14 5.3. other operations ............................................................................................................................... ..... 17 5.3.1. rosc operation ............................................................................................................................... .17 5.3.2. led operation ............................................................................................................................... .. 18 5.3.3. feed-through mode operation ....................................................................................................... 18 5.3.4. power-on playback operation ........................................................................................................ 18 5.3.5. automatic single message playback .............................................................................................. 18 5.3.6. power is interrupted abruptly .......................................................................................................... 18 6. absolute maximum ratings [1] ..............................................................................................................19 6.1. operating conditions .............................................................................................................................. 1 9 7. electrical characteristics ..............................................................................................................20 7.1. dc parameters ............................................................................................................................... ........ 20 7.2. ac parameters ............................................................................................................................... ........ 21 8. typical application circuit ................................................................................................................22 9. packaging ............................................................................................................................... ....................24 9.1. die information ............................................................................................................................... ......... 24 10. ordering information ..........................................................................................................................25 11. version history ............................................................................................................................... ........26 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 revision 0.30 1. 0 general description nuvoton?s ISD14B00 chipcorder ? series is a single-chip multiple-message record/playback series with dual operating modes with wide operating voltage ranging from 2.4v to 5.5v . the sampling frequency can be selected from 4 to 12 khz via an external resistor, which also dete rmines the duration. the device is designed for mostly standalone applications, and of course, it can be manipulated by a microcontroller, if necessary. the two operating modes are address mode and direct m ode. while in address mode, both record and playback operations are manipulated according to the start address and end address speci fied through the start address and end address pins. in direct mode, the device can configure the memory up to as many as eight similar duration messages, pending upon the fixed message c onfiguration settings. with the record or playback feature bei ng pre-selected, each message can be randomly accessed via its message control pin. the device has a selectable differential microphone input with agc feature or single-ended analog input, anain, under feed-through mode. the audio output is either a di fferential class-d pwm direct-drive or a single-ended voltage output (aux out), depending on the derivative selected. 2. 1 features the ISD14B00 is a multiple messages record/playba ck device with two operational modes: address mode and direct mode. ? ? ? ? ? ? ? ? ? ? ? ? ? ? y playback takes precedence over the re cording operationtemperature option: 0 y packaging: die only 2.1. address mode ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 revision 0.30 ? rec : level-hold or edge-trigger (toggle on-off) recording from start to end addresses. ? playe : edge-trigger playback from start to end address and stops at eom marker, if eom is prior to end address. toggle on-off. ? playl : level-hold playback from start to end address. also, if constantly low, device will loop playback from start to end address. 2.2. direct mode ? while direct mode is active, utilizing the configuration pins, fmc1 , fmc2 & fmc3, to define up to eight similar duration messages for random access. ? the control pins are: m1 ~ m8 (message activation) and r /p (record or playback selection). ? the record or playback operation is pre-defined by the r /p pin. ? each message can be randomly accessed via its message control pin ( m1 ~ m8 ) and the desired operation is facilitated accordingly. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 revision 0.30 3. 2 block diagram clock control non-volatile multi level storage array automatic gain control (agc) antialiasing filter smoothing filter amp pre- amp sp + sp - playl playe agc mic+_ anain amp s0 s1 s2 s3 e0 e1 e2 e3 rosc v cca v ssa v ssd v ccd v ssp2 v ccp v ssp1 power conditioning addr xclk device & address control rec led ft switch address trigger : direct trigger: fmc2 fmc3 m1 m2 m3 r/p m8 m6 m7 fmc1 drct m5 m4 led ft mic- v cca www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 6 - revision 0.30 4. 3 pin description pin name pin # i / o function v ssd 1 i digital ground: ground path for digital circuits. s0 [1] : in address mode, start address bit 0. s0/ m1 2 i m1 : when direct mode is active, low active operation on 1 st message. internal pull-up & debounce existed. s1 [1] : in address mode, start address bit 1. s1/ m2 3 i m2 : when direct mode is active, low active operation on 2 nd message. internal pull-up & debounce existed. s2 [1] : in address mode, start address bit 2. s2/ m3 4 i m3 : when direct mode is active, low active operation on 3 rd message. internal pull-up & debounce existed. s3 [1] : in address mode, start address bit 3. s3/ m4 5 i m4 : when direct mode is active, low active operation on 4 th message. internal pull-up & debounce existed. playl : in address mode, low active input, level-hold playback start to end addresses, debounce & internal pull-up existed. holding playl low constantly will perform looping playback function from start to end addresses with insignificant dead time between messages regardless of sampling frequencies. playl /fmc1 6 i fmc1: when direct mode is active, fmc1, together with fmc2 & fmc3 , setup various fixed-message configurations. e0 [1] : in address mode, end address bit 0. e0/ m5 7 i m5 : when direct mode is active, low active operation on 5 th message. internal pull-up & debounce existed. v ssa 8 i analog ground: ground path for analog circuits. e1 [1] : in address mode, end address bit 1. e1/ m6 9 i m6 : when direct mode is active, low active operation on 6 th message. internal pull-up & debounce existed. e2/ m7 10 i e2 [1] : in address mode, end address bit 2. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 7 - revision 0.30 pin name pin # i / o function m7 : when direct mode is active, low active operation on 7 th message. internal pull-up & debounce existed. e3 [1] : in address mode, end address bit 3. e3/ m8 11 i m8 : when direct mode is active, low active operation on 8 th message. internal pull-up & debounce existed. v ssp2 12 i ground: ground for negative pwm speaker driver. sp- 13 o sp-: negative signal of the differ ential class-d pwm speaker outputs. this output, together with the sp+, is used to drive an 8 ? speaker directly. v ccp 14 i speaker power supply: power supply for pwm speaker drivers. sp+ 15 o depending on the derivat ive selected, it could be: sp+: positive signal of the differentia l class-d pwm speaker outputs. this output, together with the sp-, is used to drive an 8 ? speaker directly. or, aux out: single-ended voltage output. v ssp1 16 i ground: ground for posit ive pwm speaker driver. agc 17 i automatic gain control (agc): the agc adjusts the gain of the preamplifier dynamically to com pensate for the wide range of microphone input levels. the agc allows the full range of signals to be recorded with minimal distortion. the agc is designed to operate with a nominal capacitor of 4.7 f connected to this pin. connecting this pin to ground (v ssa ) provides maximum gain to the preamplifier circuitry. conversely, c onnecting this pin to the power supply (v cca ) provides minimum gain to the preamplifier circuitry. mic+: non-inverting input of the differential microphone signal. mic+ / anain 18 i anain: when ft is selected, the mic+ input is configured to a single-ended input with 1vp-p maximum input amplitude and feed-through to the speaker outputs. mic- / nc 19 i mic-: inverting input of the differential microphone signal. while ft is enabled, mic- pin is disabled and must be floated. rosc 20 i oscillator resistor: connect an external resistor from this pin to v ssa to select the internal sampling frequency. v cca 21 i analog power supply: power supply for analog circuits. led 22 o led output: during recording, this output is low. also, led pulses low momentarily at the end of playback. playe : in address mode, low active input, edge-trigger playback from start to end addresses & toggle on-off. debounce & internal pull-up existed. playe /fmc2 23 i fmc2: when direct mode is active, fmc2, together with fmc1 & fmc3 , setup various fixed-message configurations. rec / r /p 24 i rec : in address mode, level-hold (after 1 sec holding) or edge-trigger (toggle on-off), low active, recording from start to end addresses. debounce & internal pull-up existed. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 8 - revision 0.30 pin name pin # i / o function r /p ( when direct mode is active): ? when r /p is set to low, level-hold record operation is selected. when r /p is set to high, edge-trigger & toggle on-off playback operation is selected. external clock: in address mode, low active and level-hold input. as xclk activated, rosc pin accepts external cl ock input signal, provided resistor at rosc must be removed. connecting this pin to high enables device running on internal clock via rosc resistor. if not used, xclk must be at high level. xclk /fmc3 25 i when direct mode is active, fmc3, together with fmc1 & fmc2 , setup various fixed-message configurations. ft 26 i feed-through: low active input, level-hold, debounce & internal pull-up required. when ft is selected, the mic+ input is configured to a single- ended input with 1vp-p maximum input amplitude and feed-through to the speaker outputs. level-hold input. addr: when set to high, the dev ice operates under address mode. addr/ drct 27 i level-hold input. drct : when set to low, the device operates under direct mode. the device reconfigures its pin definit ions to fit various fixed-message configurations utilizing fmc1 , fmc2 & fmc3 pins as below table. fmc3 fmc2 fmc1 # of fixed messages 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 v ccd 28 i digital power supply: power supply for digital circuits. notes: [1] : address bits s0, s1, s2, s3, e0, e1, e2 & e3 are used to access the memory location. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 9 - revision 0.30 5. 4 functional description there are two operational modes: address mode and di rect mode. after a new condition is selected on addr/ drct , the power must be cycled to enable it. 5.1 11 a ddress m ode the start address pins (s0, s1, s2 & s3) and end address pins (e0, e1, e2 & e3) are used to access the memory location and they can divide the memory into a maximum of 16 slots. they are defined as follows, under 8k sampling frequency: s3 ( e3 ) s2 ( e2 ) s1 ( e1 ) s0 ( e0 ) row # i14b20 duration [s] 0 0 0 0 0 0 0 0 0 1 8 1.0 0 0 1 0 16 2.0 0 0 1 1 24 3.0 0 1 0 0 32 4.0 0 1 0 1 40 5.0 0 1 1 0 48 6.0 0 1 1 1 56 7.0 1 0 0 0 64 8.0 1 0 0 1 72 9.0 1 0 1 0 80 10.0 1 0 1 1 88 11.0 1 1 0 0 96 12.0 1 1 0 1 104 13.0 1 1 1 0 112 14.0 1 1 1 1 120 15.0 s3 ( e3 ) s2 ( e2 ) s1 ( e1 ) s0 ( e0 ) row # i14b40 duration [s] 0 0 0 0 0 0 0 0 0 1 16 2.0 0 0 1 0 32 4.0 0 0 1 1 48 6.0 0 1 0 0 64 8.0 0 1 0 1 80 10.0 0 1 1 0 96 12.0 0 1 1 1 112 14.0 1 0 0 0 128 16.0 1 0 0 1 144 18.0 1 0 1 0 160 20.0 1 0 1 1 176 22.0 1 1 0 0 192 24.0 1 1 0 1 208 26.0 1 1 1 0 232 28.0 1 1 1 1 240 30.0 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 10 - revision 0.30 s3 ( e3 ) s2 ( e2 ) s1 ( e1 ) s0 ( e0 ) row # i14b80 duration [s] 0 0 0 0 0 0 0 0 0 1 32 4.0 0 0 1 0 64 8.0 0 0 1 1 96 12.0 0 1 0 0 128 16.0 0 1 0 1 160 20.0 0 1 1 0 192 24.0 0 1 1 1 224 28.0 1 0 0 0 256 32.0 1 0 0 1 288 36.0 1 0 1 0 320 40.0 1 0 1 1 352 44.0 1 1 0 0 384 48.0 1 1 0 1 416 52.0 1 1 1 0 464 56.0 1 1 1 1 480 60.0 below is an example: given sampling rate set to 6.4 khz, using the is d14b20 to record four messages: three messages of 2.5 seconds and one message of 12.5 seconds, t hen the memory can be assigned as follows: s3, s2, s1, s0 e3, e2, e1, e0 message 1 (2.5 seconds) 0 0 0 0 0 0 0 1 message 2 (2.5 seconds) 0 0 1 0 0 0 1 1 message 3 (2.5 seconds) 0 1 0 0 0 1 0 1 message 4 (12.5 seconds) 0 1 1 0 1 1 1 1 5.1.1. 18 record ( rec ) operation ? low active input: o level-hold for level-trigger or o falling edge for edge-trigger with debounce required. ? for 8khz sampling frequency, if rec is held at low for a period equal to 1 sec or more, then level recording is activated. however, if rec is pulsed low for less than 1 sec, then edge- trigger recording is initiated. ? for 6.4khz sampling frequency, if rec is held at low for a period equal to 1.25 sec or more, then level recording is activated. however, if rec is pulsed low for less than 1.25 sec, then edge-trigger recording is initiated. ? recording begins from the start address to end address and led is on. ? recording ceases whenever: www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 11 - revision 0.30 ? rec returns to high in level-hold mode or ? a subsequent low-pulse appears while in edge-trigger mode or ? when end address is reached. o then an eom marker is written at the end of message. and led is off. o then the device will automatically power down. ? this pin has an internal pull-up device. ? once rec is active, input on ft , addr/ drct , s0, s1, s2, s3, e0, e1 , e2 or e3 is illegal. rec mic+/- or anain end address led t deb t aset t stop1 t ahold t ers addr/drct figure 5-1 record?level ( rec ) function till end address rec mic+/- or anain end address led t deb t aset t stop1 stop start start t settle1 t ahold t ahold t aset t deb t deb t ers t ers addr/drct figure 5-2 record?level ( rec ) function with start and stop actions www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 12 - revision 0.30 rec mic+/- or anain end address led t deb t aset t stop1 stop start start t settle1 t ahold t deb t ahold t aset t deb t ers t ers addr/drct figure 5-3 record?edge ( rec ) function with on-off 5.1.2. 19 edge-triggered playback ( playe ) operation ? low active input, edge-trigger , toggle on-off, debounce required. ? playback begins from the start address to end address or eom, whichever occurrs first. ? at the end of message, led pulses low momentarily. o then device will automatically power down. ? during playback, a subsequent trigger terminates the playback operation. if eom marker is not encountered, then led will not pulses low momentarily. ? this pin has an internal pull-up device. ? once playe is active, input on playl , rec , ft , addr/ drct , s0, s1, s2, s3, e0 , e1, e2 or e3 is banned. playe sp+ sp- end of message led t deb t aset stop start start t settle2 t ahold t deb t eom t ahold t aset t deb addr/drct figure 5-4 playback?edge ( playe ) function 5.1.3. 20 level-triggered playback ( playl ) operation ? low active input, level-hold, debounce required. ? once active, playback begins from the start address and stops whenever playl returns to high. when an eom is encountered, led pulses low momentarily. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 13 - revision 0.30 o then device will automatically power down. ? this pin has an internal pull-up device. ? once playl is active, input on playe , rec , ft , addr/ drct , s0, s1, s2, s3, e0 , e1, e2 or e3 is prohibited. part of message playl sp+ sp- end of message led t deb t aset stop start start t settle2 t ahold t ahold t aset t eom t deb t deb addr/drct figure 5-5 playback?level ( playl ) function ? holding playl low constantly will perform looping play back function, without power down, from start address to end address. playl t deb t aset t ahold sp+ sp- led t eom t eom addr/drct figure 5-6 looping playback function via playl 5.1.4. 21 playback (supersedes record) operation ? playback takes precedence over the recording operation. ? if either playe or playl is activated during a recording cycl e, the recording immediately ceases with an eom marker attached, and without power down, playback of the just-recorded message performs accordingly. then device powers down. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 14 - revision 0.30 led mic+/- or anain playe sp+ sp- rec t deb t ahold t aset t settle1 t deb t eom t settle3 t ers addr/drct figure 5-7 an example of playback supersedes record 5.1.5. 22 xclk feature ? when precision sampling frequency is required, ex ternal clock mode can be activated by setting xclk to low. under such condition, the resistor at rosc pin must be removed and the external clock signal must be applied to the rosc pin. t hese conditions must be satisfied prior to any operations. ? however, when internal clock is used, xclk must be linked to high. ? the external clock frequencies required for various sampling frequencies are listed in below table. sampling freq [khz] 12 8 6.4 5.3 4 xclk [mhz] 3.072 2.048 1.638 1.356 1.024 5.2. 12 d irect m ode ? the direct mode is selected by the drct pin. once chosen, the supply voltage must be reset to allow the device to construct itself to the appropr iate configuration by re-defining the function on the related control pins. also, the mode change is only allowed while the device is in power down state and is inhibited when an operation is in progress. ? once direct mode is activated, fmc1, fmc2 & fm c3 are utilized to select various (1 to 8) fixed message configurations [1] . pending upon the arrangement on fmc1, fmc2 & fmc3, each divided message has approximate equal length of durati on, which is related to the number of rows assigned as in tables below. ? the record or playback oper ation is pre-defined by the r /p pin. setting this pin to low allows record operation while setting it to high enables playback operation. ? each message can be randomly accessed via its message control pin ( m1 ~ m8 ) and the desired operations are facilitated accordingly. non-conf igured pins are automatically disabled and must be floated. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 15 - revision 0.30 notes: [1] : number of fixed message arrangement wi th respect to fmc1, fmc2 & fmc3. fmc3 fmc2 fmc1 # of fixed messages [1] 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 [2] : number of memory row arrangement with respect to different number of fixed messages for isd14b20 (128 rows). the non-configured message control pins (mx) will be disabled. # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 128 2 64 64 3 44 42 42 4 32 32 32 32 5 26 26 26 26 24 6 23 21 21 21 21 21 7 20 18 18 18 18 18 18 8 16 16 16 16 16 16 16 16 for isd14b40 (256 rows) # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 256 2 128 128 3 86 85 85 4 64 64 64 64 5 52 51 51 51 51 6 43 43 43 43 42 42 7 37 37 37 37 36 36 36 8 32 32 32 32 32 32 32 32 for isd14b80 (512 rows) # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 512 2 256 256 3 172 170 170 4 128 128 128 128 5 103 103 102 102 102 6 86 86 85 85 85 85 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 16 - revision 0.30 7 74 73 73 73 73 73 73 8 64 64 64 64 64 64 64 64 [3] : the durations for various fixed message conf igurations on i14b20 device at 8 khz sampling frequency are shown in below table. # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 16 2 8 8 3 5.5 5.25 5.25 4 4.0 4.0 4.0 4.0 5 3.25 3.25 3.25 3.25 3.0 6 2.875 2.625 2.625 2.625 2.625 2.625 7 2.50 2.25 2.25 2.25 2.25 2.25 2.25 8 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 for isd14b40 (256 rows) # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 32 2 16 16 3 10.75 10.62 5 10.62 5 4 8.0 8.0 8.0 8.0 5 6.5 6.375 6.375 6.375 6.375 6 5.375 5.375 5.375 5.375 5.25 5.25 7 4.625 4.625 4.625 4.625 4.5 4.5 4.5 8 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 for isd14b80 (512 rows) # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 64 2 32 32 3 21.5 21.25 21.25 4 16.0 16.0 16.0 16.0 5 12.87 5 12.87 5 12.75 12.75 12.75 6 10.75 10.75 10.62 5 10.62 5 10.62 5 10.62 5 7 9.25 9.125 9.125 9.125 9.125 9.125 9.125 8 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 17 - revision 0.30 33 example of four fixed-message configuration: mic+/- or anain led fm3 fm2 fm1 m1 ~ m4 start start stop end of duration r / p t fset t deb t settle1 t deb t deb t stop1 t ers t ers addr/drct figure 5-8 record operation under fmc mode sp+ sp- led fm3 fm2 fm1 m1 ~ m4 stop start end of message r / p start t fset t deb t deb t deb t eom t settle2 addr/drct figure 5-9 playback operation under fmc mode 5.3. 13 o ther o perations 5.3.1. 23 rosc operation ? when the r osc varies from 53.3 k ? to 160 k ?, the sampling frequency changes from 12 to 4 khz accordingly. ? when r osc resistor value is changed during playback, the tone of a recorded message will alter either faster or slower. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 18 - revision 0.30 ? if the ground side of r osc resistor is floated or tied to v cc , then the current operation will be freezed. ? the operation will resume when the resistor is connected back to ground. 5.3.2. led 24 operation ? led turns on during recording. also, led pulses low at the end of message. the low period must be sufficiently greater than debounce time. 5.3.3. 25 feed-through mode operation ? as ft is held low, the mic+ pin will be reconfi gured as anain input, and the anain signal will be transmitted to the speaker outputs. under this mode, mic- pin is not used (must be floated). ? after ft is enabled, if rec is triggered, then anain signal will be recorded into memory while the feed-through path remains on. ? if ft is already enabled, activating either playe or playl will first disable the ft path and then play the recorded message. once playback completes, ft path will be resumed. ? during an operation, activating the ft pin is not allowed. 5.3.4. 26 power-on playback operation ? if playe is kept at low during power turns on, the device plays message once, then powers down. ? if playl is held at low during power turns on and constantly maintained at low, the device will play the message repeatedly, with insignifi cant dead time between messages regardless of sampling frequencies. this status will sustain unless power is turned off or playl somehow returns to high. 5.3.5. 27 automatic single message playback ? if led is connected to playe , once playe is triggered, the device plays message repeatedly without power down between the l ooping playback. however, if playe is triggered again during playback, then playback will stop 5.3.6. 28 power is interrupted abruptly ? during the device is in operation, it is st rongly recommended that the supply power cannot be interrupted. otherwise, it may cause the device to become malfunctioning. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 19 - revision 0.30 6. 5 absolute maximum ratings [1] absolute maximum ratings condition value junction temperature 150c storage temperature range -65c to +150c voltage applied to any pins (v ss ? 0.3v) to (v cc + 0.3v) voltage applied to input pins (current limited to +/-20 ma) (v ss ? 1.0v) to (v cc + 1.0v) voltage applied to output pins (current limited to +/-20 ma) (v ss ? 1.0v) to (v cc + 1.0v) v cc ? v ss -0.3v to +7.0v [1] stresses above those listed may cause perm anent damage to the devic e. exposure to the absolute maximum ratings may affect device re liability and performance. functional operation is not implied at these conditions. 6.1. 14 o perating c onditions operating conditions condition value operating temperature range 0c to +50c operating voltage (v cc ) [1] +2.4v to +5.5v ground voltage (v ss ) [2] 0v [1] v cc = v cca = v ccd [2] v ss = v ssa = v ssd www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 20 - revision 0.30 7. 6 electrical characteristics 7.1. 15 dc p arameters parameter symbol min [2] typ [1] max [2] units conditions input low voltage v il 0.3xvcc v input high voltage v ih 0.7xvcc v output low voltage v ol 0.3xvcc v i ol = 4.0 ma [3] output high voltage v oh 0.7xvcc v i oh = -1.6 ma [3] standby current i stby 1 10 a [4] [5] record current i rec 20 30 ma v cc = 5.5v [4] [5] playback current i play 20 30 ma v cc = 5.5v, no load [4] [5] pull-up device for rec , playe , playl , ft & m1 ~ m8 pins r pu1 600 k mic+ input resistance r micp 18 k ? mic- input resistance r micn 18 k ? anain input resistance r anain 42 k ? mic differential input v in1 15 300 mv peak-to-peak anain input v in2 1 v peak-to-peak gain from mic to sp+/- a msp 6 40 db v in = 15~300 mvp-p, agc = 4.7 f, v cc = 2.4v~5.5v gain from anain to sp+/- a asp 0 db v cc = 2.4v~5.5v output load impedance r spk 8 ? speaker load 670 mw v dd = 5.5 v 313 mw v dd = 4.4 v 117 mw v dd = 3 v speaker output power pout 49 mw v dd = 2.4 v 1vp-p, 1 khz sine wave at anain. r spk = 8 ? speaker output voltage v out1 v dd v r spk = 8 ? speaker, typical buzzer total harmonic distortion thd 1 % 15 mv p-p 1 khz sine wave, cmessage weighted notes: [1] typical values @ v cc = 5.5v, t a = 25 and sampling frequency (fs) at 8 khz, unless stated. [2] not all specifications are 100 per cent tested. all min/max limits ar e guaranteed by nuvoton via design, electrical testing and/or characterization. [3] led output during recording. [4] v cca , v ccd and v ccp are connected together. also, v ssa , v ssd , v ssp1 and v ssp2 are linked together. [5] all required control pins must be at appropriate status. external components are biased under a separated power supply. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 21 - revision 0.30 7.2. 16 ac p arameters characteristic [1] symbol min [2] typ max [2] unit s conditions sampling frequency fs 4 12 khz [3] record duration t rec 10.6 32 sec [3] playback duration t play 10.6 32 sec [3] debounce time t deb 225k/f s msec [3] [4] address setup time t aset 30 nsec address hold time t ahold 225k/f s msec [3] [4] fmc setup time t fset 30 nsec record settle time t settle1 32k/fs msec [3] [4] play settle time t settle2 256k/f s msec [3] [4] delay from record to play t settle3 128k/f s msec [3] [4] record stop time t stop1 30 nsec led pulse low time t eom 256k/f s msec [3] [4] notes: [1] conditions are v cc = 5.5v, t a = 25 c and sampling frequency (f s ) at 8khz, unless specified. [2] not all specifications are 100 per cent tested. all min/max limits ar e guaranteed by nuvoton via design, electrical testing and/or characterization. [3] when different f s is applied, the value will change accordingly. also, stability of internal oscillator may vary as much as + 10% over the operating tem perature and voltage ranges. [4] k = 1000. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 22 - revision 0.30 8. 7 typical application circuit the following typical application examples on isd14b 00 series are for references only. they make no representation or warranty that such applicati ons shall be suitable for the use specified. it?s customer?s obligation to verify the design in its own system for the functi onalities, voice quality, current consumption, and etc. in addition, the below notes apply to the following application examples: ? the suggested values are for references onl y. depending on system r equirements, they can be adjusted for functionalities, voice quality and degree of performance. it is important to have a separate path for each ground and power back to the related terminals to minimize the noise. besides, the power supplie s should be decoupled as close to the device as possible. also, it is crucial to follow good audio design practices in layout and power supply decoupling. see recommendations in application notes from our websites. example #1: operations via star t and end address under address mode. rosc* speaker v cc 4. 7 f* ? 4.7 k 0.1 f* 0. 1 f* 4.7 k ? 4.7 k ? 4.7 f* 1 k d1 0.1 f 10 f* v ccd 0.1 f 10 f* v cca 10 f* v ccp 0.1 f 10 f* 0.1 f v cca v ccd v ccp vcc gnd ISD14B00 v ssd mic+_anain mic- sp- v ccd agc rosc v cca sp+ v ssa playe playl s2 s1 s0 e2 e1 e0 v ccp v ssp1 v ssp2 addr ft xclk led rec e3 s3 to switches or address i/os www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 23 - revision 0.30 example #2: fixed message configurat ion operations under direct mode. rosc* speaker v cc 4. 7 f* ? 4.7 k 0.1 f* 0. 1 f* 4.7 k ? 4.7 k ? 4.7 f* 1 k d1 0.1 f 10 f v cca 10 f* v ccp 0.1 f 10 f* 0.1 f v cca v ccd v ccp vcc gnd ISD14B00 fmc1 fmc3 fmc2 m3 m4 m5 m6 m7 m8 m2 r/p m1 mic+_anain mic- sp- agc rosc sp+ v ssp1 v ssp2 ft v ssd v ccd v cca v ssa v ccp drct 0.1 f 10 f* v ccd led v cc 34 good audio design practices nuvoton?s chipcorder are very high-quality singl e-chip voice recording and playback devices. to ensure the highest quality voice reproduction, it is important that good audio design practices on layout and power supply decoupling are followed. see application information links below for details. good audio design practices http://www.nuvoton-usa.com/pr oducts/isd_products/chipcorder /applicationinfo/apin11.pdf single-chip board layout diagrams http://www.nuvoton-usa.com/pr oducts/isd_products/chipcorder /applicationinfo/apin12.pdf it is strongly recommended that before any design or la yout project starts, t he designer should contact nuvoton sales rep for the most update technical information and layout advice. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 24 - revision 0.30 9. 8 packaging 9.1. 17 d ie i nformation 14b00 v ccd v ssd s1 / m2 s2 / m3 addr/drct ft xclk / fmc3 rec / r/p s0 / m1 rosc mic- agc playe / fmc2 led playl / fmc1 sp+ sp- v ccp v ssp2 mic+_anain v cca v ssp1 v cca s3 / m4 e0 / m5 e1 / m6 e2 / m7 v ssa e3 / m8 contact nuvoton sales representat ives for other information. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 25 - revision 0.30 10. 9 ordering information product number descriptor key i14bxxx x product series: 14b = 14b00 duration: 20 : 10.6 ? 32 secs 40 : 21.3 ? 64 secs 80 : 42.6 ? 128 secs product name: i = isd temperature : blank = commercial ? die (0 c to +50 c) package type : x = die when ordering ISD14B00 devices, please refer to the above ordering scheme. contact the local nuvoton sales representatives for any questions and the availability. for the latest product information, please contact the nuvoton sales/rep or access nuvoton?s worldwide web site at http://www.nuvoton-usa.com www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 26 - revision 0.30 11. 10 version history version date description 0 sep 21, 2007 initial revision 0.1 oct 10, 2007 update block diagram 0.2 oct 16, 2007 update description 0.21 nov 07,2008 change to nuvoton logo update application circuit 0.30 jan 19, 2009 rename norm/ mode to addr/ drct . www.datasheet.co.kr datasheet pdf - http://www..net/
ISD14B00 publication release date: jan 19, 2009 - 27 - revision 0.30 nuvoton products are not designed, int ended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or fo r other applications intended to support or sustain life. furthermore, nuvoton produc ts are not intended for applications wher ein failure of nuvoton products could result or lead to a situation wherein personal injury, deat h or severe property or environmental damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulti ng from such improper use or sales. the contents of this document are provided only as a guide for the applications of nuvoton products. nuvoton makes no representation or warranties with respect to the accuracy or completeness of the c ontents of this publication and reserves the right to discontinue or make changes to specif ications and product descriptions at any time without notice. no license, whether express or implied, to any intellectual property or other right of nuvoton or others is granted by this publication. except as set forth in nuvoton's standard terms and conditions of sale, nuvoton assumes no liability whatsoever and disclaims any express or implied warrant y of merchantability, fitness for a particular purpose or infringement of any intellectual property. the contents of this document are pr ovided ?as is?, and nuvoton assumes no liability whatsoever and disclaims any express or implied warranty of merchant ability, fitness for a particular purpose or infringement of any intellectual property. in no event, shall nuvoton be liable for any damages whatsoever (including, wit hout limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if nuvoton has been advis ed of the possibility of such damages. application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and nuvoton makes no representation or warranty that such applications sha ll be suitable for the use specified. the 100-year retention and 100k record cycle projections are based upon accelerated reliability tests, as published in the nuvoton reliability report, and are neither warranted nor guaranteed by nuvo ton. this product incorporates superflash ? . information contained in this isd ? chipcorder ? datasheet supersedes all data fo r the isd chipcorder products published by isd ? prior to august, 1998. this datasheet and any future addendum to this datasheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentat ion contains information in addition to the information in this, the information contained herein supersedes and governs su ch other information in its entirety. this datasheet is subject to change without notice. copyright ? 2005, nuvoton electronics corporation. all rights reserved. chipcorder ? and isd ? are trademarks of nuvoton electronics corporation. superflash ? is the trademark of silicon storage technology, inc. all other trademarks are p ro p erties of their res p ective owners. 29 headquarters nuvoton technology corporation america technology electronics (shanghai) ltd. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 yan an w. rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http:// www.nuvoton-usa.com/ http://www.nuvoton.com.tw/ taipei office nuvoton technology corporation japan nuvoton technology (h.k.) ltd. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg. 3-7-18 unit 9-15, 22f, millennium city, neihu district shinyokohama kohokuku, no. 378 kwun tong rd., taipei, 114 taiwan yokohama, 222-0033 kowloon, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/

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